Author

Killian Pluenet

C/C++ developer, embedded systems & low-level

Killian Pluenet is a C/C++ developer specialized in embedded systems and low-level programming. He builds firmware on STM32 architectures and spends his time working out what actually happens under the hood, from communication between components to resource optimization in constrained environments. He is a member of Sophia Hack Lab, the hackerspace in Antibes.

Alongside that he develops Memtide, a RAM and CXL memory orchestrator: a subject that combines fine-grained memory management, modern architectures and performance at a very low level. It is that same lens (memory, bandwidth, what happens beneath the abstractions) that he brings to LeCompute: dissecting AI compute from the silicon to the code, without the hype.

Personal site: killianpluenet.com

  • C / C++
  • Embedded systems
  • Low-level programming
  • Memory architecture & CXL

Articles by Killian in English 31

Costs

LLM inference cost: when can a GPU beat an API?

Calculate API and self-hosted inference costs with a fixed quality target, input/output mix, full operating cost and a server capacity check.

4 min read
  • Inference cost
  • GPU cloud
  • LLM APIs
  • Self-hosting

Kernel & Perf

NVIDIA Minerva: finding what slows down an AI cluster

An AI job can slow down without a GPU failing outright. Minerva connects infrastructure and workload signals to help operators investigate the dependencies behind that slowdown.

10 min read
  • NVIDIA Minerva
  • Observability
  • GPU
  • NCCL

Kernel & Perf

Scion: why Anthropic replaced Git for its agents

An agent finishes a patch, then waits for test machines to fetch the code. Scion provides a starting point for understanding that hidden cost and the infrastructure choices behind it.

8 min read
  • Scion
  • Anthropic
  • Git
  • AI agents

Silicon

800 VDC: why AI data centers are rewiring their power

A single GPU rack already draws more than 2,000 amps. At 1 MW, today's 54 V distribution would need close to 20,000: here is why NVIDIA and the hyperscalers are moving to 800 V DC, and what remains unsolved.

26 min read
  • 800 VDC
  • Data center power
  • NVIDIA Kyber
  • Vera Rubin

Runtimes

NVIDIA PAIR: when more machines make local AI faster

Your GPU is busy while another computer sits idle. NVIDIA PAIR can send it requests, but whether you finish sooner depends on how the work is shared.

14 min read
  • NVIDIA PAIR
  • Local LLM
  • Ollama
  • LM Studio

Silicon

Ryzen AI Halo vs DGX Spark: What 128GB Doesn't Tell You

Ryzen AI Halo and DGX Spark both offer 128 GB, but performance changes with model and protocol. Vendor claims and independent LLM tests, audited.

17 min read
  • Ryzen AI Halo
  • DGX Spark
  • Ryzen AI Max+ 395
  • Local LLM

Silicon

BlueField-4 vs Pensando Salina: the DPU enters the inference data path

BlueField-4 and Pensando Salina compute no tokens. They move networking, storage, security and selected KV-cache transfers away from the host CPU. Here is the data path that can free the GPU, or merely move the bottleneck.

11 min read
  • BlueField-4
  • Pensando Salina
  • DPU
  • KV Cache

Costs

MLPerf Endpoints: can inference providers finally be compared?

MLPerf Endpoints measures an inference service through its API at several load levels. Version 0.7 finally traces the curve between throughput, TTFT, TPOT and quality, but it does not normalize cost yet.

12 min read
  • MLPerf
  • LLM Inference
  • Benchmark
  • TTFT

Silicon

UALink 2.0 vs NVLink 6: when the network computes all-reduce

UALink 2.0 standardizes compute inside the network; NVLink 6 integrates it into its switches. Here is what the mechanism changes, and why Helios and Vera Rubin still cannot be ranked.

14 min read
  • UALink 2.0
  • UALoE
  • NVLink 6
  • in-network compute

Runtimes

DWDP for MoE inference: move weights, not tokens

Expert parallelism moves tokens to weights. DWDP reverses the path, prefetching remote expert weights and removing cross-rank synchronization. The bet works inside a narrow regime.

11 min read
  • DWDP
  • MoE
  • SGLang
  • TensorRT-LLM

Silicon

RTX PRO 6000 or three RTX 5090s: 96 GB is not one memory pool

An RTX PRO 6000 and three RTX 5090s each add up to 96 GB of GDDR7. For an LLM, that is where the equality ends: one pool, one sharded model and three independent replicas pay different costs.

10 min read
  • RTX PRO 6000
  • RTX 5090
  • Local LLM
  • multi-GPU

Runtimes

vLLM 0.27 turns the KV cache into peer-to-peer memory

vLLM 0.27 lets every engine serve CPU-resident KV blocks to another peer over NIXL, filters tiers per request and emits routable cache events. The mechanism is shipped; the production speedup is not proven.

11 min read
  • vLLM 0.27
  • KV cache
  • NIXL
  • Offloading

Silicon

RTX Spark on Windows: CUDA is native, the LLM stack is not yet

RTX Spark brings up to 128 GB of unified memory and native CUDA to Windows on Arm. As of August 12, CUDA remains a developer preview, TensorRT-RTX is ready, and the LLM serving stack still needs qualification.

11 min read
  • RTX Spark
  • Windows on Arm
  • CUDA 13.4
  • TensorRT-RTX

Runtimes

Kimi K3 opens 2.8T parameters, not a local model

Kimi K3 activates 104 billion parameters out of 2.8 trillion, mixes KDA with MLA across a one-million-token context, and needs an eight-B300 or eight-MI355X node in vLLM's launch recipes.

9 min read
  • Kimi K3
  • Moonshot AI
  • MoE
  • KDA

Silicon

How much VRAM do you need to run an LLM locally?

How much VRAM does a local LLM need? The ~2 GB per billion parameters rule, the weight of the KV cache, what quantization changes, and what actually fits on your card.

8 min read
  • VRAM
  • Local LLM
  • Quantization
  • KV cache