One number on the box, two different promises
AMD shows Ryzen AI Halo ahead of DGX Spark on four LLMs. A few weeks later, AMD publishes a more detailed agent benchmark: Halo still finishes first, but Spark completes the generation stage 22.3 seconds earlier. AMD’s overall lead comes from the stages before generation. This is not a contradiction. The two charts do not measure the same thing.
That distinction is the real comparison. Ryzen AI Halo here means AMD’s developer platform with a Ryzen AI Max+ 395, not every mini PC based on Strix Halo. DGX Spark means NVIDIA’s complete GB10 system. Both place 128 GB of LPDDR5X near the CPU and GPU. Almost everything else diverges.
| Ryzen AI Halo | DGX Spark | |
|---|---|---|
| CPU | Ryzen AI Max+ 395, 16 Zen 5 cores, 32 threads, x86-64 | GB10, 20 Arm cores, arm64 |
| Accelerator | Radeon 8060S, 40 RDNA 3.5 CUs, XDNA 2 NPU | Integrated Blackwell GPU, 6,144 CUDA cores |
| Physical memory | 128 GB unified LPDDR5X | 128 GB coherent LPDDR5X |
| Memory bandwidth | 256 GB/s | 273 GB/s |
| Advertised peak | 60 FP16 TFLOPS | 1 FP4 PFLOP with sparsity |
| Storage | 2 TB M.2 self-encrypting SSD | 1 TB or 4 TB NVMe SSD, depending on SKU |
| Networking | 10 GbE | 10 GbE and 2 ConnectX-7 ports, up to 200 Gb/s line rate per port |
| US list price | $3,999 | $4,699 for the 4 TB Founders Edition |
128 GB is not 128 GB of VRAM
On a discrete graphics card, VRAM belongs to the GPU. Here, the CPU, GPU, operating system, buffers and KV cache The stored key and value vectors an LLM has already computed for every token it has processed. It avoids recomputing attention over the whole history, at the cost of a memory footprint that grows with the context length. draw from the same physical pool. A model can avoid copying data across PCIe, but it does not receive 128 GB of reserved space.
AMD documents the distinction in concrete terms. On Windows, Variable Graphics Memory (VGM) assigns 64 GB to the GPU by default and can rise to 96 GB. On Linux, AMD’s vLLM playbook lists 96 GB of shared memory by default. ROCm documentation separately describes a Graphics Translation Table (GTT) ceiling near half of system RAM before tuning; after configuration, llama.cpp can report close to 120,000 MiB available. These figures describe three layers: reservation, driver limit and memory finally exposed to the runtime.
On Spark, CPU and GPU share the same DRAM without a fixed GPU partition, apart from a 2 GB display reservation that DGX OS can configure to 4 GB. The operating system can reclaim or migrate pages, and NVIDIA warns that memory reported as free does not always reflect all reclaimable memory. On both machines, 128 GB answers how much memory is physically installed?, not how much can my model take?.
Bandwidth creates a second difference: 273 GB/s on Spark versus 256 GB/s on Halo. Spark’s theoretical lead is 6.6%. It is real, but too small to explain a large gap in an end-to-end agent. CPU work, backend behavior and intermediate copies can weigh more heavily in total time than those 17 GB/s.
Model structure matters too. All four workloads in AMD’s chart are MoE Mixture-of-Experts. An architecture where the network is split into many experts, of which a router activates only a small subset per token. Per-token compute follows the number of active parameters; memory follows the total count, since every expert must stay resident in VRAM, ready to be called. models. In an execution where the full model remains resident, capacity must hold every expert, but only a subset is activated for each token. During decode, the system still reads active experts, attention layers, any shared experts and the KV cache, but it does not traverse every inactive expert on every token. A result on GLM-4.7-Flash-30B-A3B or Qwen3.5-122B-A10B therefore cannot be extended to a similarly sized dense model.
A token also crosses a software stack
Halo uses an x86 CPU with 16 cores and 32 threads, and can run Windows 11 or Linux. As of September 4, 2026, ROCm 10.0 lists Ryzen AI Max+ 395 and its Radeon 8060S under the gfx1151 LLVM target. PyTorch 2.13 is documented, and vLLM 0.27 supports the iGPU on Linux. llama.cpp can run through ROCm or Vulkan. AMD documents SGLang 0.5.15 in its broader ecosystem, but its compatibility matrix does not list gfx1151 among the supported SGLang targets. Saying that ROCm supports the hardware does not mean every framework and model is validated on this machine.
Spark runs DGX OS 7.5, based on Ubuntu 24.04 arm64, with CUDA 13. NVIDIA provides container images, a vLLM stack, TensorRT-LLM and a llama.cpp path for sm_121. That integration removes work for a workload already built around CUDA Compute Unified Device Architecture. NVIDIA's GPU computing platform: language, compiler and libraries (cuBLAS, cuDNN). Its software ecosystem is the main lock-in against alternatives like ROCm; at runtime, its context also reserves an incompressible slice of VRAM. , but not all of it. An x86-64-only image needs an arm64 variant or an arm64 rebuild. TensorRT-LLM validates architectures and precisions model by model. NVIDIA’s vLLM notes also document cases where users must cap the unified pool with --gpu-memory-utilization 0.7 to avoid an out-of-memory failure.
Halo’s XDNA 2 NPU does not decide any benchmark examined here. AMD did not use it in the Halo versus Spark comparisons. AMD documents compatible ONNX workloads for the NPU, but crediting it for these published gains would invent a mechanism that the protocol never activated.
| Ryzen AI Halo | DGX Spark | |
|---|---|---|
| Host architecture | x86-64 | arm64 |
| Operating systems | Windows 11, Linux | DGX OS 7.5 |
| GPU stack | ROCm 10.0, Vulkan | CUDA 13 |
| Documented servers | vLLM 0.27 on Linux, llama.cpp | vLLM NGC, TensorRT-LLM, llama.cpp |
| Main caveat | SGLang 0.5.15 matrix excludes gfx1151 | 1.2 validates beta single-node support; multi-node uses a 1.3 preview |
AMD’s four bars prove less than the headline
AMD’s first Halo benchmark awards it four wins in tokens per second. The surface reading looks decisive.
| Model | Structure | Claimed Halo lead |
|---|---|---|
| GLM-4.7-Flash-30B-A3B | MoE, about 3B active | +14% |
| gpt-oss-120B | MoE, 5.1B active | +7% |
| Qwen3.5-122B-A10B | MoE, 10B active | +12% |
| Qwen3.6-35B-A3B | MoE, about 3B active | +4% |
The problem is not that these four numbers must be false. It is that they answer a question too narrow to drive a purchase. AMD specifies a 100-token context and an average of three runs. The page publishes neither absolute tokens per second, variance, output length, concurrency, runtime commit nor an exact checksum for the weights. It compares a preproduction Halo platform with a DGX Spark whose status is not specified.
Without those details, we cannot tell whether the gap comes from prefill The opening phase of LLM inference: prompt tokens are processed in parallel to build the context state. That reuse raises arithmetic intensity and can make the phase compute-bound; the exact regime depends on the model, batch, context and backend. , decode The autoregressive generation phase of an LLM: one token is produced at a time while rereading weights and the relevant context state. At low batch sizes, that traffic can make decode memory-bandwidth-bound. Its share of total cost still depends on input and output lengths, batching and cache reuse. , a backend, a memory setting or a fixed cost. The absence of a dense model closes another shortcut: these gains do not show that Halo reads a dense 70B more efficiently.
NVIDIA separately publishes 55.37 generation tokens/s for gpt-oss-120B in MXFP4 under llama.cpp, with a 2,048-token input, 128-token output and batch size 1. That number is absolute, but it cannot sit next to AMD’s percentages. Context, output, quantization and stack do not match. Combining the charts would create a benchmark that never happened.
Two independent tests redraw the result
Two reviews published on July 6, 2026 add the missing outside evidence, without creating a universal leaderboard. Tom’s Hardware used the same Unsloth GGUF GPT-Generated Unified Format. llama.cpp's file format that stores the tensors, their quantization types, the vocabulary and the model metadata in a single file. Its aligned layout lets it be read with mmap, so the model starts in a fraction of a second. Q4_K_M files and llama.cpp endpoints for Qwen3.6-35B-A3B, Gemma 4 12B and gpt-oss-120B. Halo could not launch Qwen3.6 through its preinstalled vLLM stack, so the reviewer fell back to llama.cpp. The Dell Pro Max GB10 comparator generally delivered better generation throughput, and Halo’s time to first token deteriorated more sharply as context grew.
This is strong evidence against treating AMD’s four bars as a general Halo victory, but it is not a direct DGX Spark chassis comparison. Dell’s system uses the same GB10 SoC, while cooling, firmware and software packaging can still differ. Tom’s Hardware also notes that prompt caching could shrink the worst first-token gaps. The result supports a mechanism, not an interchangeable product identity.
HotHardware compared Halo with an actual DGX Spark using its open-source Local AI Bench through Ollama-style interfaces at 8K, 32K and 64K prefill lengths. The two systems were neck and neck on Llama 3.1 8B. Halo trailed Spark only slightly on Qwen3-14B, ran about 30% slower in generation on gpt-oss-20B, roughly matched Spark on Qwen3.6-35B-A3B and edged it on Llama 3.1 70B Q4. At 64K, Halo even held a small generation lead on Qwen3.6 while Spark took longer to start.
The independent evidence therefore rules out both easy conclusions. It does not confirm an overall Halo win, and it does not establish an overall Spark win. HotHardware measures complete products through their usable stacks rather than isolating silicon, while Tom’s GB10 machine is not the exact DGX Spark product. Together, the reviews show that model choice, context length, prompt processing and runtime can reverse the ranking.
HEPA changes the question, not the facts
AMD’s second test is more useful because it opens the box. HEPA, short for Hermes Executive Presentation Agent, ingests 302 sources split into 801 chunks, processes them, then asks Qwen3.6-35B-A3B, described as 4-bit without a more precise format, to produce a presentation. AMD reports five valid runs and 25 deterministic checks. Seven of eight stages are primarily CPU work in AMD’s aggregate, including embedding and routing; final generation uses the GPU.
| Stage | Ryzen AI Halo | DGX Spark |
|---|---|---|
| Preparation and CPU stages | 152.1 s | 229.9 s |
| Text generation | 159.5 s | 137.2 s |
| Complete workflow | 311.6 s | 367.1 s |
Halo finishes the workflow 55.5 seconds earlier. Spark nevertheless finishes generation 22.3 seconds earlier. The first statement describes the complete system; the second describes the phase closest to a GPU inference benchmark. Both are true, and their coexistence reveals what a single total score hides.
AMD says it keeps the same corpus, the same model advertised as 4-bit and the same high-level settings. Yet the published configuration gives --ctx-size 65536 only for Halo and commit 9bebfcb only for llama-server on Spark, without the equivalent detail for the other system. That configured ceiling does not reveal the prompt’s actual token count. Halo uses Vulkan with the Mesa RADV driver, --threads 16, --threads-batch 32 and --parallel 1; Spark uses CUDA with 20 threads, 20 batch threads and the same concurrency of 1. The exact 4-bit format, prompts, checksums and variance are not public. HEPA therefore compares two systems tuned to complete a task, not two isolated GPUs under a controlled experiment.
The test establishes one useful fact: in this benchmark, Halo completes AMD’s aggregate CPU stages faster, including embedding and routing, enough to erase its delay during generation. The protocol cannot isolate the role of architecture, vectorization, thread count or software. It proves neither a general x86 CPU advantage, nor Radeon 8060S superiority, nor Vulkan superiority over CUDA. An agent does not benchmark a GPU. It crosses a machine.
What the price buys around the model
AMD lists Halo at $3,999 in the United States, sold officially through Micro Center and limited to the US market. NVIDIA lists the 4 TB DGX Spark Founders Edition at $4,699. The gap is $700 before sales tax, shipping, warranty differences or any import cost outside the United States.
Halo includes a 2 TB M.2 self-encrypting SSD, 10 GbE, Wi-Fi 7 and a familiar x86 host. Spark is offered with 1 TB or 4 TB of SSD storage; the Founders Edition used for this price comparison has 4 TB. It also includes two ConnectX-7 ports with a line rate up to 200 Gb/s per port. That figure guarantees neither 400 Gb/s of aggregate application throughput nor the same rate inside a workload. NVIDIA joins Spark systems over Ethernet using RDMA over Converged Ethernet (RoCE) on those ports, not through external NVLink. NVLink-C2C connects CPU and GPU inside GB10.
The network does not turn two 128 GB pools into transparent 256 GB VRAM. The runtime partitions work and exchanges data between nodes. Still, a 200 Gb/s line rate gives Spark far more communication headroom than Halo’s 10 GbE for tensor parallelism or a distributed pipeline. Conversely, a local application rich in x86-only dependencies, CPU parsing or Windows tooling encounters less porting friction on Halo.
Choose by finding the slow stage
For a workflow close to HEPA, Halo has a measured end-to-end advantage: its CPU stages finish early enough to decide total time. Independent replication is still required before extending that result to document agents as a category. Windows or Linux support and the x86 host can reduce porting cost when a dependency already targets that platform.
For a stack already built around CUDA, Spark retains the structural advantage. NVIDIA containers, TensorRT-LLM, vLLM and ConnectX-7 form a more integrated product for serving, testing and scaling a supported workload. The validation level must stay explicit: TensorRT-LLM 1.2 validates beta support on a single Spark, while NVIDIA’s two-Spark playbook uses preview 1.3 images. Spark’s faster generation stage in HEPA points in the same direction, without generalizing to every model.
When exact tokens per second decide the purchase, neither vendor chart is enough. Test the precise weights, target context and expected concurrency. Usable capacity can eliminate one machine before the benchmark starts. NVIDIA’s “up to 200B” ceiling explicitly assumes FP4; AMD’s depends on the quantized footprint and GPU-addressable memory. Neither promises universal support or comfortable throughput after adding the cache.
The comparable protocol still missing
A reproducible comparison would first pin the model repository and commit, tokenizer, quantization, GGUF GPT-Generated Unified Format. llama.cpp's file format that stores the tensors, their quantization types, the vocabulary and the model metadata in a single file. Its aligned layout lets it be read with mmap, so the model starts in a fraction of a second. checksum, llama.cpp commit, drivers and sampling parameters. The exact same artifact would run on both machines. The experiment would then separate software fairness from product value: one pass with the same runtime, followed by one pass with each platform’s best native backend.
| Variable | Values to publish |
|---|---|
| Models | one dense and one MoE; repository, commit, tokenizer, quantization and checksum |
| Input | 128, 4,096 and 32,768 tokens |
| Output | fixed at 256 tokens |
| Concurrency | 1 and 4 requests |
| Repetitions | stable thermal state, 2 warm-ups, then at least 30 runs for a p95 |
| State | cold and warm runs separated, cache policy disclosed |
| Generation | fixed seed, temperature and sampling parameters |
| Metrics | prefill, decode, time to first token (TTFT) with tokenization scope, per-token latency, median, p95 |
| Resources | available memory, peak memory and wall energy over a defined window |
That protocol would expose the boundary both campaigns currently blur. The first pass would measure hardware under a common constraint. The second would measure each product as buyers can actually use it, with its ecosystem working on its behalf.
Conclusion
The next credible comparison should not chase one total score. It should trace time from raw document to final token, then publish every stage. As local agents combine retrieval, parsing, embeddings, tool calls and generation, that decomposition will matter more than the compute peak printed on a spec sheet.
Halo and Spark already move the debate: capacity lets the model enter, but the system decides whether it becomes useful. The first vendor to publish full traces, checksums and wall energy may not win every bar. It will win the comparison engineers can reproduce.
Sources and method
Scope. This article compares the AMD Ryzen AI Halo developer platform with Ryzen AI Max+ 395, not every Strix Halo computer, against the NVIDIA DGX Spark with GB10. Sources and availability were checked on September 4, 2026. This is an English adaptation of the French original, not a literal translation.
Verified facts. Halo’s 16-core CPU, Radeon 8060S, 128 GB, 256 GB/s, 2 TB M.2 self-encrypting SSD, 10 GbE and listed 120 W TDP come from the AMD product sheet. The 60 FP16 TFLOPS claim comes from the Halo overview, while the 45 W to 120 W configurable range comes from the Ryzen AI Max+ 395 chip page. Spark’s 20-core Arm CPU, 128 GB, 273 GB/s, 1 TB or 4 TB SSD, 140 W SoC, 240 W power supply and ConnectX-7 ports come from the NVIDIA hardware guide. Internal NVLink-C2C and coherent memory are specified in the DGX Spark datasheet; external Ethernet and RoCE topology come from the clustering guide.
Memory and software. Halo VGM settings, shared memory and vLLM support come from AMD’s vLLM playbook, user guide and ROCm 10 RDNA 3.5 optimization guide. ROCm 10.0, PyTorch, vLLM and SGLang status comes from AMD’s release notes and compatibility matrix. The ROCm and Vulkan paths in llama.cpp come from AMD’s LM Studio playbook. DGX OS and CUDA versions come from the Spark release notes, which also document the 2 GB or 4 GB display reservation. Unified-memory caveats come from Spark known issues. arm64 porting and sm_121 come from the NVIDIA porting guide. TensorRT-LLM beta status and validated configurations come from its release notes. The vLLM allocation caveat comes from the NGC vLLM 26.07 notes.
Vendor measurements. The four 4% to 14% differences, three-run average, 100-token context and Halo’s preproduction status come from the Ryzen AI Halo page, tests SHO-57 and SHO-61. SHO-57 says “Qwen 3.6B Model” in its note while the chart names Qwen3.6-35B-A3B; this article uses the chart’s precise model name. HEPA timings, CPU versus generation split, 4-bit model, Spark-side commit and partially published settings come from AMD’s August 3, 2026 technical post. These remain vendor measurements, not independent validation. NVIDIA’s gpt-oss-120B result at ISL 2,048, OSL 128 and batch 1 comes from its DGX Spark benchmark. It is not combined with AMD’s protocol.
Independent measurements. Tom’s Hardware tested the same Unsloth Q4_K_M files through llama.cpp on Halo and a Dell Pro Max GB10, and reported throughput plus time-to-first-token behavior at longer contexts. The Dell is evidence about the same GB10 SoC, not a claim that its complete system is identical to DGX Spark. HotHardware compared Halo directly with DGX Spark using the author’s open-source Local AI Bench at 8K, 32K and 64K prefill lengths. Its published prose supports the directional findings and the roughly 30% gpt-oss-20B generation gap reported here; chart values that were not available as text are not reproduced.
Model architectures. gpt-oss-120B has 117 billion total parameters and 5.1 billion active parameters per token according to OpenAI. The other three workloads are documented by their model cards: GLM-4.7-Flash-30B-A3B, Qwen3.5-122B-A10B and Qwen3.6-35B-A3B. All four workloads in AMD’s chart are MoE models, so the article does not extrapolate them to dense models.
Prices. Halo’s $3,999 US price comes from SHO-61 on the AMD product page; US-only Micro Center distribution comes from AMD’s availability announcement. The 4 TB DGX Spark Founders Edition was listed at $4,699 on the NVIDIA US Marketplace when checked. Prices can change and exclude sales tax.
Assumptions and limitations. Spark’s bandwidth lead is calculated as (273 - 256) / 256 = 6.64%; it does not predict an application by itself. The HEPA stage times reconstruct AMD’s totals exactly, but AMD does not provide the complete corpus, prompts, checksums or variance. The two independent reviews compare products through different software paths, and Tom’s uses another GB10 system rather than a DGX Spark enclosure. Table 5 is a LeCompute recommendation, not a benchmark already run.
Image credit. Original illustration generated for LeCompute. Both enclosures are intentionally generic and do not reproduce either product exactly.
