On September 17 in Shanghai, Huawei presented a machine whose ambition becomes clearer when you look at its connections. Atlas 960E is intended to bring together up to 4,096 NPU Neural Processing Unit. An accelerator specialised in neural network operations. Depending on its design and software, it can support inference, training or both. Supported operators and numerical formats depend on the hardware. accelerators from the Ascend family in a tightly coupled system. Huawei promises to move data between them more efficiently, using optical interconnects integrated into its UnifiedBus architecture.
For large AI models, that is a substantial problem to solve. Buying more accelerators does not guarantee that training finishes sooner. When chips spend part of their time waiting for data or for other chips, some of their theoretical compute capacity goes unused. Huawei wants to reduce that wait.
Can competition move from the chip to the whole system? That question connects the announcement to what customers need. It also requires a distinction between what Huawei has presented, what its software can exploit and what NVIDIA already builds at this scale.
Thousands of chips have to work together
A large model can distribute its computation across several accelerators. Each processes part of the workload, then passes on results that others need before they can continue. Communication time becomes part of the time required to finish the computation.
This is particularly visible in MoE Mixture-of-Experts. An architecture where the network is split into many experts, of which a router activates only a small subset per token. Per-token compute follows the number of active parameters; memory follows the total count, since every expert must stay resident in VRAM, ready to be called. models. They route each piece of text to selected subsets of model parameters, called experts. When those experts sit on different chips, the runtime has to deliver data to the right destinations and collect the results. A fast accelerator can end up waiting because transfers take too long or one expert receives more work than its neighbours.
Huawei proposes to make a group of machines behave as a more closely integrated system. UnifiedBus is intended to let components communicate through a common protocol and access memory beyond their physical server. That broadens the options for placing data. Distance still matters: a shared address space does not give every memory location the same access latency.
The distinction matters commercially. More memory helps only if software can use it without spending the expected gain on moving data. The architecture has to place useful resources close together and organise transfers as well as make them addressable.
Our analysis of expert models and their network explains how these transfers affect serving.
Optics become part of the machine
Atlas 960E uses Hi-ONE, an optical engine based on near-packaged optics, or NPO Near-Packaged Optics. Integration that places optical elements close to the electronic circuits they connect to, shortening electrical paths and changing link density and maintenance requirements. . This approach brings optical components closer to the electronic circuits they connect to. It changes how links are integrated, with implications for power consumption, density and maintenance.
Huawei says that 5,500 Hi-ONE engines would replace the 48,000 800G optical modules required by its reference architecture. It claims a power reduction of more than 550 kW. That figure belongs to Huawei’s interconnect comparison. It describes neither the total power consumption of Atlas 960E nor a measured saving against an NVIDIA system. September 17 announcement.
The announcement also shows how broadly Huawei defines its product. Accelerators, communication and physical integration are designed together. Buyers are being asked to evaluate a complete machine and its operating choices, rather than select each component separately.
The commercial demonstration is still ahead
The roadmap puts a limit on what the presentation establishes. Huawei schedules Ascend 960DT for the first quarter of 2027 and 960PR for the third. Announcing Atlas 960E does not demonstrate that a customer already runs the advertised configuration in production.
Its most striking compute-utilisation claim needs a separate qualification. Huawei reports a 2.75-fold improvement in a simulation of a 100,000-NPU cluster organised into large groups of 4,000 NPUs instead of eight-chip servers. This compares two ways of organising computation. It does not measure a lead over an NVIDIA machine. David Wang’s presentation.
Huawei does have a documented precedent. The CloudMatrix384 paper describes running DeepSeek-R1 and separating input processing from response generation. It reports results for a particular hardware configuration, model and service constraints. That provides evidence of a measurable system implementation on that generation. Its results do not automatically transfer to Atlas 960E. CloudMatrix384 study.
Software determines what the customer gets
Hardware architecture needs an execution layer. An inference runtime distributes the model, selects optimised operations and arranges communication. This is where a hardware capability becomes a practical gain, or an integration problem.
The vLLM-Ascend 0.23.0 release notes show that work in progress. They describe dependencies for A2, A3 and Ascend 950, alongside combinations that remain limited. For DeepSeek V4 on A2/A3 under high concurrency, they identify spikes in time between tokens during recompilation of Triton kernels, the small programs that execute operations on the accelerator. That limitation applies to those configurations, not to Atlas 960E. Release notes.
For a customer, such behaviour can matter more than peak compute. An interactive API needs a steady response; training needs sustained progress. Time spent adapting models, diagnosing slowdowns and recovering from failures belongs in the system evaluation.
NVIDIA already competes at this scale
Huawei faces a competitor that also sells a complete architecture. DGX Vera Rubin NVL72 combines GPUs, CPUs and NVLink NVIDIA's proprietary GPU-to-GPU interconnect. NVLink 5 (Blackwell) reaches 1.8 TB/s bidirectional per GPU; NVLink 6 (Rubin) doubles that to 3.6 TB/s. With NVSwitch, it accelerates GPU-to-GPU transfers and collectives; memory remains physically distributed, and remote access does not have the cost of local HBM. interconnects in an integrated system. Competition already includes how effectively these components work together. NVIDIA product page.
Counting accelerators cannot settle that comparison. A larger installation also commits more memory, electrical power, space and equipment to maintain. What matters is the work it completes within a given time and quality requirement, relative to the resources it consumes.
Huawei’s approach is a credible way to compete: improve how computation is organised when a single-chip comparison leaves much of the story untold. Its commercial advantage will depend on how much of that efficiency customers can reproduce.
The next useful evidence for Atlas 960E will be identified deployments and complete results: model, numerical precision, latency, system energy and sustained reliability. Huawei’s promise deserves to be examined at system scale. The evidence has to arrive at that scale too.
Sources and method
This analysis uses sources reviewed as of September 20, 2026. Announcements, specifications and schedules are attributed to Huawei’s Atlas 960E announcement and David Wang keynote release. Their publication is verified; LeCompute has not independently measured the claimed commercial performance.
The experimental precedent is the CloudMatrix384 paper, version 3. The software review covers vLLM-Ascend 0.23.0. NVIDIA’s competing strategy is documented in its DGX Vera Rubin NVL72 product page. No performance ratio between these systems is calculated.
The explanation of communication and the proposed comparison criteria are technical analysis. LeCompute tested none of this hardware for this article. Roadmap statements reflect the sources available on September 20, 2026.
